Dae Hyun Kim (Resume )      Last update: 2.9.2012.

Education


Work Experience
Publications - Journals
  1. Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim, "Methodology to Determine the Impact of Linewidth Variation on Chip Scale Copper/Low-k Backend Dielectric Breakdown," Microelectronics Reliability, Vol. 50, Issue 9-11, pp. 1341-1346, 2010. (pdf)

  2. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling," IEEE Transactions on Components, Packaging, and Manufacturing Technology (TCPMT), Vol. 1, No. 2, pp. 168-180, 2011. (pdf)
  3. Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim, "Impact of Irregular Geometries on Low-k Dielectric Breakdown," Microelectronics Reliability, Vol. 51, Issue 9-11, pp. 1582-1586, 2011. (pdf)
  4. Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay, "Pre-bond and Post-bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System," IEEE Transactions on Components, Packaging, and Manufacturing Technology (TCPMT), Vol. 1, No. 11, pp. 1718-1727, 2011. (pdf)
Publications - Conferences
  1. Dae Hyun Kim and Sung Kyu Lim, "Bus-Aware Microarchitectural Floorplanning," 13th IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), pp. 204-208, 2008. (pdf)
  2. Dae Hyun Kim and Sung Kyu Lim, "Global Bus Route Optimization with Application to Microarchitecture," 26th IEEE International Conference on Computer Design (ICCD), pp. 658-663, 2008. (pdf)

  3. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "TSV-aware Interconnect Length and Power Prediction for 3D Stacked ICs," 12th IEEE International Interconnect Technology Conference (IITC), pp. 26-28, 2009. (pdf)
  4. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs," 11th ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), pp. 85-92, 2009. (pdf)
  5. Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim, "A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout," 27th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 674-680, 2009. (pdf)

  6. Dae Hyun Kim and Sung Kyu Lim, "Through-Silicon-Via-aware Delay and Power Prediction Model for Buffered Interconnects in 3D ICs," 12th ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), pp. 25-31, 2010. (pdf)
  7. Dae Hyun Kim, Yen-Kuan Wu, Rasit Topaloglu, and Sung Kyu Lim, "Enabling 3D Integration Through Optimal Topography," 4th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y), pp. 70-73, 2010. (pdf)
  8. Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay, "Design Method and Test Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System," 28th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 694-697, 2010. (pdf)
  9. Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory," 23rd IEEE Custom Integrated Circuits Conference (CICC), 2010. (pdf)
  10. Muhammad Bashir, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor, "TDDB Chip Reliability in Copper Interconnects," 18th IEEE International Integrated Reliability Workshop (IIRW), pp. 121-124, 2010. (pdf)

  11. Taigon Song, Chang Liu, Dae Hyun Kim, Jonghyun Cho, Joohee Kim, Jun So Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon and Sung Kyu Lim, "Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs," 12th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 122-128, 2011. (pdf)
  12. Muhammad Bashir, Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim, and Linda Milor, "Backend Low-k TDDB Chip Reliability Simulator," 49th IEEE International Reliability Physics Symposium (IRPS), pp. 2C.2.1-2C.2.10, 2011. (pdf)
  13. Dae Hyun Kim and Sung Kyu Lim, "Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D ICs," 14th IEEE International Interconnect Technology Conference (IITC), 2011. (pdf)
  14. Dae Hyun Kim, Suyoun Kim, and Sung Kyu Lim, "Impact of Nano-scale Through-Silicon Vias on the Quality of Today and Future 3D IC Designs," 13th ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2011. (pdf)
  15. Dae Hyun Kim and Sung Kyu Lim, "A Study on the Impact of Nano-Scale TSVs on 3D IC Designs," SRC TECHCON Conference, 2011
  16. Dae Hyun Kim, Rasit Topaloglu, and Sung Kyu Lim, "TSV Density-driven Global Placement for 3D Stacked ICs," 8th International SoC Design Conference (ISOCC), pp. 135-138, 2011 (invited) (pdf)

  17. Dae Hyun Kim, Rasit Topaloglu, and Sung Kyu Lim, "Block-level 3D IC Design with Through-Silicon-Via Planning," 17th IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), 2012. (pdf)
  18. Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim, "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory," to appear in 59th IEEE International Solid-State Circuits Conference (ISSCC), 2012. (pdf)
  19. Kaiyuan Yang, Dae Hyun Kim, and Sung Kyu Lim, "Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices," to appear in 13th IEEE International Symposium on Quality Electronic Design (ISQED), 2012. (pdf)
  20. Chang-Chih Chen, Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim, "Backend Dielectric Chip Reliability Simulator for Complex Interconnect Geometries," to appear in 50th IEEE International Reliability Physics Symposium (IRPS), 2012. (pdf)

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