I am a PhD candidate at Georgia Tech working in the area of computer architecture
for
Dr. Sudhakar Yalamanchili.
As such, this page mostly deals with my research interests.
I am currently investigating how commodity interconnects (HT, QPI, PCIe,
Ethernet, Infiniband) can be used to support more efficient memory and
accelerator (GPU) sharing across cluster and data center nodes. In short,
I've been working on creating a hardware-based, non-coherent Global Address
Space (GAS) that can be used to improve both the performance and power efficiency
of a limited amount of DRAM or limited number of accelerators in HPC clusters
or data centers. This work has led in part to two specifications with the HyperTransport
Consortium and a detailed simulation-based reference model for HyperTransport over
Ethernet.
Some of my previous research has included work on interconnects for
FPGA-based accelerators. This work is still in progress by Dr. Sass at his
Reconfigurable Computing Systems (RCS) lab at the University of North Carolina, Charlotte (UNCC).
Other interests include working with the Linux kernel as well as
computer and network security on a system and cluster level.